PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 219

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

1. Introduction
PNX15xx/952x Series includes a PCI interface for easy integration into personal
computer applications (where the PCI-bus is the standard for high-speed
peripherals). In embedded applications the PCI bus can interface to peripheral
devices that implement functions not provided by the on-chip modules or to
connected several CPUs together.
The main function of the PCI interface is to connect the PNX15xx/952x Series on-
chip MTL bus (and therefore its main memory) and its internal registers to the rest of
the world. A bus cycle on PCI that targets an address mapped into PNX15xx/952x
Series memory space will cause the PCI interface to create a MTL bus cycle targeted
at DRAM. From PNX15xx/952x Series, only the TM3260 CPU can cause the PCI
interface to create PCI bus cycles; the other on-chip modules cannot see external
hardware through the PCI interface. From PCI, DRAM and most of the registers in
MMIO space can be accessed by external PCI initiators.
The PCI interface implements DMA (also called block or burst transfers) and non-
DMA transfers. DMA transfers are interruptible on 64-byte boundaries. The PCI
interface can service outbound (PNX15xx/952x Series
PNX15xx/952x Series) data flows simultaneously.
The following classes of operations invoked by PNX15xx/952x Series cause the PCI
interface to act as a PCI initiator:
The PNX15xx/952x Series PCI interface responds as a target to external initiators for
a limited set of PCI transaction types:
PNX15xx/952x Series ignores PCI transactions other than the above.
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Chapter 7: PCI-XIO Module
PNX15xx/952x Series Data Book – Volume 1 of 1
Rev. 4.0 — 03 December 2007
Transparent, single-word (or smaller) transactions caused by TM3260 loads and
stores to one of the two available the PCI address aperture, PCI1 and PCI2.
Explicitly programmed single-word I/O or configuration read or write transactions
Explicitly programmed multi-word DMA transactions.
Configuration read/write.
Memory read/write, read line, and read multiple to the PNX15xx/952x Series
DRAM or MMIO apertures.
PCI) and inbound (PCI
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