PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 809

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
5. Example: Audio In—Programmer’s View
Table 4: Precise Mapping Audio In Sample Time and Bits to Memory Bytes
PNX15XX_PNX952X_SER_N_4
Product data sheet
Operating Mode
8-bit mono—little-endian or big-endian
8-bit stereo—little-endian or big-endian
16-bit mono—little-endian
16-bit mono—big-endian
16-bit stereo—little-endian
16-bit stereo—big-endian
Figure 5:
8-bit
mono
8-bit
stereo
16-bit
mono
16-bit
stereo
Audio In Memory Data Structure (Programmer’s View)
addr
left
addr
left
n
n
addr
left
addr
left
The PNX15xx/952x Series Audio In module receives mono or stereo, 8 or 16-bit/
sample audio data and fills memory with an 8 or 16-bit data structure. The data
structure is put in memory according to both endian mode laws.
A programmer’s view of the Audio In function is sketched in
programmer sees the address of each item (according to the DMA rule), and expects
that 16-bit values are correctly stored in memory according to the CPU law. The DMA
logic of the Audio In module therefore needs to write data in memory (byte) locations
precisely, per
registers of the Audio In module per
the same bit-layout in the CPU register, regardless of endian mode.
n
n
•
•
addr+1
left
addr+1
right
Swap over 16 bits
Swap over 32 bits
n+1
n
Table
addr+2
left
addr+2
left
n+2
n+1
Rev. 4.0 — 03 December 2007
addr+2
left
addr+2
right
4. Note the programmer also sees the Control and Status
m[addr]
left
left
left
left
left
left
n+1
n
n
n
n
n
n
n
addr+3
left
addr+3
right
[7:0]
[7:0]
[7:0]
[15:8]
[7:0]
[15:8]
n+3
n+1
addr+4
left
addr+4
left
Figure
n+4
n+2
m[addr+1]
left
right
left
left
left
left
addr+4
left
addr+4
left
n+1
n
n
n
n
[15:8]
[7:0]
[15:8]
[7:0]
n
n+2
n+1
[7:0]
[7:0]
6. These registers are always seen with
addr+5
left
addr+5
right
n+5
n+2
PNX15xx/952x Series
m[addr+2]
left
left
left
left
right
right
addr+6
left
addr+6
left
n+2
n+1
n+1
n+1
n+6
n+3
n
n
Chapter 29: Endian Mode
[7:0]
[15:8]
[7:0]
[7:0]
[7:0]
[15:8]
Figure
addr+6
left
addr+6
right
n+3
n+1
addr+7
left
addr+7
right
© NXP B.V. 2007. All rights reserved.
5. The
n+7
n+3
m[addr+3]
left
right
left
left
right
right
n+3
n+1
n+1
n+1
n
n
[15:8]
[7:0]
[7:0]
[15:8]
[7:0]
[7:0]
29-809