PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 153

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
XTALO
XTALI
dds_tst_bypass
Clock Module Block Diagram
(analog pad)
clk_dds_tst
sel_div_tst
pll1_7_fb
oscillator
pad
en
xtal_clk
Figure 1
(DFT) have been added into the drawing and can be disregarded for functional
behavior. The signals in
functional operating mode.
Custom Analog Block (CAB)
low jitter PLL (external to CAB)
DDS
1.728 GHz
PLL2
shows a block diagram of the Clock Module. Additional Design For Test
/2
DDS0
DDS1
DDS2
DDS3
DDS4
DDS5
DDS6
DDS7
DDS8
Rev. 4.0 — 03 December 2007
bypass dds
clk_mem
DIVIDER
DIVIDER
PLL0
red
PLL1
slice_test_in
are for ATE purpose and are disabled in normal
MSB in DDSx_CTL
registers selects test input
on DDS
slice
slice
tps_clocks
tst_clk_mem
tst_clk_fpi
DFT LOGIC
MMIO-Interface
Control Regs
PNX15xx/952x Series
&
Chapter 5: The Clock Module
slice_test_out
© NXP B.V. 2007. All rights reserved.
ccb_si
ccb_so
tst_clk_enable
tst_clk
tst_cab_bypass
tst_ccb_shift
RESET_IN_N
5-153