PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 776

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

1. Introduction
2. Functional Description
1.1 Features
All the memory traffic of PNX15xx/952x Series modules is centralized into an internal
Hub, through the MTL bus, before it gets to the main memory interface module. In
addition to this network function, the HUB includes a generic arbiter for memory
bandwidth allocation.
Remark: The arbiter only deals with module memory traffic and not with CPU memory
traffic which is handled by the Main Memory Interface module, see
Controller. This is different approach than the PNX1300 Series arbiter.
The key features of the HUB are:
The Arbiter module is used as an arbiter between different DMA channel clusters.
Inside these clusters traffic from related DMA channels of Peripherals are combined
by applying round-robin arbitration. (see
arbitrated DMA channels).
The arbitration engine combines Time-Division Multiple Access (TDMA), priority, and
round-robin methods; resulting in a guaranteed and high-level quality of service. The
arbitration engine ensures programmable maximum latency and programmable
minimal bandwidth to the unified resource. It also makes sure that best effort agents
are fairly granted when higher priority agents do not request the channel.
The priority table can be dynamically altered by software. Two priority tables are
implemented from which the inactive table can be changed on-the-fly. The Arbiter
hardware takes care of smooth switching between the two tables.
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Chapter 26: Memory Arbiter
PNX15xx/952x Series Data Book – Volume 1 of 1
Rev. 4.0 — 03 December 2007
Provides a hierarchical memory access network that connects module DMA
ports to a single access port of the Main Memory interface. DMA agents, i.e. the
PNX15xx/952x Series modules are organized in clusters.
Includes simple round-robin sub-arbitration for lower levels of hierarchy
Provides sophisticated intermediate arbitration for upper levels of the network
hierarchy
Default settings allow each module to have access to the memory but may not fit
latency requirement as soon as many modules are turned on simultaneously
Table 1
for a list of clusters and sub-
Product data sheet
Chapter 9 DDR