PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 147

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
3. Timing Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 4:
module clocks
sys_rst_out_n
1. POR_IN_N is asserted for 100 s (min) after power stable. peri_rst_n and jtag_rst_n follows the assertion and the
2. All module resets sync to 27 MHz and all modules are reset at the same time. The Boot script can now kick off.
3. The boot script program switches to the default frequencies for the CPU and the DRAM clocks.
4. CPU and DRAM clocks are blocked in the clock module to ensure safe, glitch less switch over from initial 27 MHz.
5. Once the TM3260 has been released from reset it can release the sys_rst_out_n signal for external peripherals.
POR_IN_N
release of POR_IN_N. The Clock module kicks off 27 MHz clock to all modules.
peri_rst_n
jtag_rst_n
POR_IN_N Timing and Reset Sequence
Vdd
3.1 The Hardware Timing
Remark: Upon any of the described ways to reset the PNX15xx/952x Series system
the sys_rst_out_n remains asserted until a write with 0x1 occurs to the
RST_CTL.REL_SYS_RST_OUT bit.
The assertion of POR_IN_N or RESET_IN_N signals causes the assertion of
peri_rst_n, sys_rst_out_n and jtag_rst_n (only when POR_IN_N is asserted). See
Figure
the PNX15xx/952x Series modules receive the 27 MHz crystal oscillator input. The
27 MHz clock remains active for all the modules until the registers in the Clock
module are programmed to switch from 27 MHz to their functional module clocks
(either by the boot scripts or by the TM3260). The use of this generic 27 MHz clock
allow all the modules to be reset synchronously.
After de-asserting the RESET_IN_N pin, the peri_rst_n is also de-asserted and all
modules release their internal resets synchronously. The PLLs come up to their
default values while POR_IN_N or RESET_IN_N are asserted. The Clock module will
safely (i.e. glitch free) switch clocks from the 27 MHz clock to the separate module
functional clocks.
Figure 4
is exactly the same when RESET_IN_N is asserted except that in that case the
jtag_rst_n signal is not asserted.
trst = 100 s (min)
4. When the Clock module receives the peri_rst_n signal, it ensures that all
details the hardware reset. Only POR_IN_N is shown. The reset sequence
1
Rev. 4.0 — 03 December 2007
27 MHz
2
3
PNX15xx/952x Series
Released by a write to
REL_SYS_RST_OUT
Clocks switched
by Boot module
4
5
© NXP B.V. 2007. All rights reserved.
Chapter 4: Reset
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