PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 295

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
PNX15XX_PNX952X_SER_N_4
Product data sheet
15:4
3:2
1:0
Offset 0x10,4064 -> 0x070
31:24
23:16
15:8
Bit
Symbol
INTERVAL
EVENT_MODE
FIFO_MODE
IO_SEL_3
IO_SEL_2
IO_SEL_1
IO_SEL
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
a
<0-3>
Value
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Interval of silence. If a change is monitored on a signal and no more
signal activity is monitored for a time equal to the interval of silence,
writing to the current buffer is halted and a BUFx_RDY interrupt is
generated. Writing continues to the alternate buffer.
This field is only valid if FIFO_MODE[1:0] = 00.
0x000 - Disabled
0x001 - 1x128 13.5 MHz period, 9.48 s
0x002 - 2x128 13.5 MHZ periods, 18.96 s
0x003 - 3x128 13.5 MHZ periods, 28,44 s
....
0x3FF - 1023x128 13.5 MHz periods, 9.69 ms
....
0xFFF - 4095x128 13.5 MHz periods, 38.8 ms
Note: This field in only valid in Event Timestamping mode
(FIFO_MOD E = 00 and EVENT_MODE != 00)
Timestamping event mode:
NOTE: This field is valid in Event Timestamping mode
(FIFO_MODE[1:0]=00)
This bit selects what mode of operation the FIFO queue is in:
00 - Event Timestamping (or Disabled if EVENT_MODE[1:0] = 00)
01 - Signal Sampling
10 - Pattern Generation using timestamps.
11 - Pattern Generation using samples.
This field selects a GPIO pin which should be merged with the
GPIO pin selected by IO_SEL_0, IO_SEL_1 and IO_SEL_2 to
enable 4-bit samples in one FIFO queue.
Note: This field is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
This field selects a GPIO pin which should be merged with the
GPIO pins selected by IO_SEL_0, IO_SEL_1 and IO_SEL_3 to
enable 4-bit samples in one FIFO queue.
Note: This field is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
This field selects a GPIO pin which should be merged with the
GPIO pin selected by IO_SEL_0 to enable 2-bit samples in one
FIFO queue.
Note: This field is only used in Signal Sampling mode and Pattern
Generation using samples mode and is enabled by EN_IO_SEL
00 - event detection disabled
01 - capture negative edge
10 - capture positive edge
11 - capture either edge
Chapter 8: General Purpose Input Output Pins
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
8-295