PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 329

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 8:
controller
SDRAM
Controller
SDRAM
Examples of Supported Memory Configurations
DDR
DDR
3.2 Error Signaling
3.3 Latency
clk/clkn
cmd
DQ
D[31:0]
DQ[3:2]
D[31:16]
DQ[1:0]
D[15:0]
clk/clkn
cmd
The MMIO port does not support error signaling. Reads from invalid addresses return
the value “0”, writes to invalid addresses are ignored. The errors are not reported at
system level.
Changing MMIO registers of an initiated DDR SDRAM Controller may cause incorrect
behavior. Forcing the DDR controller into halt mode, programming MMIO registers
while in halt mode, then unhalting the DDR controller when the MMIO registers have
been programmed is the suggested series of actions to take.
The DDR SDRAM Controller uses two pipeline stages to calculate the command(s)
that will be issued to the DDR memories after a MTL command is accepted by the
DDR controller.
We will describe the latency of a MTL read command. Assume we have a MTL read
command on one of the MTL ports in cycle 0 which is accepted by the DDR
controller. In cycle 1, the DDR controller will determine the first DDR burst for the MTL
read command. In cycle 2, the DDR SDRAM Controller will determine the DDR
commands that need to be sent out on the DDR interface (we assume we do not have
Single Rank
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
x16
x16
x32
Rev. 4.0 — 03 December 2007
controller
SDRAM
Controller
SDRAM
DDR
DDR
DQ
D[31:0]
DQ[3:2]
D[31:16]
DQ[1:0]
D[15:0]
clk/clkn
cmd
clk/clkn
cmd
PNX15xx/952x Series
Two Ranks of Memories
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
x16
x16
x32
Chapter 9: DDR Controller
clk/clkn
clk/clkn
cmd
cmd
© NXP B.V. 2007. All rights reserved.
SDRAM
SDRAM
SDRAM
DDR
DDR
DDR
x16
x16
x32
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