PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 185

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04,7008
Reset values set for expected frequencies for faster boot-up, shorter boot code.
31:30
29
28
27:24
23:21
20:12
11:10
9:4
3:2
1
0
Offset 0x04,700C
31:3
2
1:0
DDS Registers
Offset 0x04,7010
31
30:0
Offset 0x04,7014
31
30:0
Offset 0x04,7018
31
30:0
Symbol
Reserved
Turn Off Acknowledge
PLL Lock
pll2_adj
Reserved
pll2_n
Reserved
pll2_m
Reserved
pll2_pd
Reserved
Reserved
pll1_7ghz_pd
Reserved
Enable
dds0_ctl[30
Enable
dds1_ctl[30:0]
Enable
dds2_ctl[30:0]
:0]
PLL2_CTL
PLL1_7GHZ_CTL
DDS0_CTL
DDS1_CTL
DDS2_CTL
Acces
s
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
…Continued
Value
-
-
-
0
-
0x2E
-
0x5
-
0
-
-
0
-
0
0x07684
bd0
0
0x04000
000
0
0x04000
000
Rev. 4.0 — 03 December 2007
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Indicates that during a frequency change that the clock has been
driven low.
A one indicates that the PLL is locked
Current adjustment.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
9-bit N parameter to PLL2.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6-bit M parameter to PLL2.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1: powerdown PLL2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1: powerdown PLL1_7GHZ
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS0 control (default = 50 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS1 control (default = 27 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS2 control (default = 27 MHz)
Section 2.2.1 on page
Section 2.2.1 on page
Section 2.2.1 on page
PNX15xx/952x Series
Chapter 5: The Clock Module
5-158.
© NXP B.V. 2007. All rights reserved.
5-158.
5-158.
5-185