M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 


Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
2.5
Output Disable (GD)
The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at
V
, the outputs are driven by the Output Enable. When Output Disable, GD, is at V
IH
outputs are high impedance independently of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as there is no internal pull-up resistor to drive
the pin.
2.6
Write Enable (W)
The Write Enable, W, input controls writing to the command interface, Address inputs and
Data latches. Both addresses and data can be latched on the rising edge of Write Enable
(also see Latch Enable, L).
2.7
Reset/Power-down (RP)
The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware
reset is achieved by holding Reset/Power-down Low, V
inhibited to protect data, the command interface and the program/erase controller are reset.
The status register information is cleared and power consumption is reduced to deep power-
down level. The device acts as deselected, that is the data outputs are high impedance.
After Reset/Power-down goes High, V
after a delay of t
PHEL
If Reset/Power-down goes Low, V
aborted, in a time of t
During power-up power should be applied simultaneously to V
at V
. When the supplies are stable RP is taken to V
IL
and Write Enable, W, should be held at V
In an application, it is recommended to associate reset/power-down pin, RP, with the reset
signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is
performing an erase or program operation, the memory may output the status register
information instead of being initialized to the default asynchronous random read.
See
Table 22: Reset, power-down and power-up AC characteristics
power-down and power-up AC waveforms - control pins
2.8
Latch Enable (L)
The bus interface can be configured to latch the address inputs on the rising edge of Latch
Enable, L, for asynchronous latch enable controlled read or write or synchronous burst read
operations. In synchronous burst read operations the address is latched on the active edge
of the Clock when Latch Enable is Low, V
without affecting the address used by the memory. When Latch Enable is Low, V
is transparent. Latch Enable, L, can remain at V
operations.
, the memory will be ready for bus read operations
IH
or bus write operations after t
PHWL
, during a Block Erase, or a Program the operation is
IL
maximum, and data is altered and may be corrupted.
PLRH
during power-up.
IH
. Once latched, the addresses may change
IL
for asynchronous random read and write
IL
Signal descriptions
, for at least t
. Writing is
IL
PLPH
.
and V
with RP held
DD
DDQ(IN)
. Output Enable, G, Chip Enable, E,
IH
and
Figure 17: Reset,
low, for more details.
, the latch
IL
, the
IL
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