M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 

Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Table 5.
Asynchronous read electronic signature operation
Code
Manufacturer
Device
Burst configuration
register
1. BCR = Burst configuration register.
3.2
Synchronous bus operations
For synchronous bus operations refer to
3.2.1
Synchronous burst read
Synchronous burst read operations are used to read from the memory at specific times
synchronized to an external reference clock.
In the M58BW016FT and M58BW016FB only, once the memory is configured in burst
mode, it is mandatory to have an active clock signal since the switching of the output buffer
data bus is synchronized to the active edge of the clock. In the absence of clock, no data is
output.
Caution:
The M58BW016DT and M58BW016DB are not concerned by the paragraph above.
The burst type, length and latency can be configured. The different configurations for
synchronous burst read operations are described in
register. Refer to
In continuous burst read, one burst read operation can access the entire memory
sequentially by keeping the Burst Address Advance B at V
clock cycles. At the end of the memory address space the burst read restarts from the
beginning at address 000000h.
A valid synchronous burst read operation begins when the Burst Clock is active and Chip
Enable and Latch Enable are Low, V
the internal burst address counter on the valid Burst Clock K edge (rising or falling
depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first.
After an initial memory latency time, the memory outputs data each clock cycle (or two clock
cycles depending on the value of M9). The Burst Address Advance B input controls the
memory burst output. The second burst output is on the next clock valid edge after the Burst
Address Advance B has been pulled Low.
Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the burst
controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low
on the active clock edge, no new data is available and the memory does not increment the
internal address counter at the active clock edge even if Burst Address Advance, B, is Low.
Device
E
G
All
V
V
IL
IL
M58BW016DT
V
V
IL
IL
M58BW016FT
M58BW016DB
V
V
IL
IL
M58BW016FB
V
V
IL
IL
Table 6
Figure 4
and
Figure 5
for examples of synchronous burst operations.
. The burst start address is latched and loaded into
IL
Bus operations
GD
W
A18-A0
V
V
00000h
IH
IH
V
V
00001h
IH
IH
V
V
00001h
IH
IH
V
V
00005h
IH
IH
together with the following text.
Section 3.3: Burst configuration
for the appropriate number of
IL
DQ31-DQ0
00000020h
00008836h
00008835h
(1)
BCR
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