M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 

Specifications of M58BW016DB80T3F

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M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Table 7.
Burst configuration register
Bit
M15
M14
M13-M11
M10
M9
M8
Valid data ready
M7
M6
Valid clock edge
M5-M4
M3
M2-M0
1. X latencies can be calculated as: (t
number from 4 to 8, t
calculation).
2. This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for
the M58BW016D version only if the operative frequency is below 45 MHz.
3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.
4. Y latencies can be calculated as: t
Description
Value
0
Synchronous burst read
Read select
1
Asynchronous read (default at power-on)
0
Reserved (default value)
000
Reserved (default value)
001
Reserved
010
4, 4-1-1-1
(3)
011
5
, 5-1-1-1, 5-2-2-2
(1)
X-Latency
(3)
100
6
, 6-1-1-1, 6-2-2-2
(3)
101
7
, 7-1-1-1, 7-2-2-2
(3)
110
8
, 8-1-1-1, 8-2-2-2
111
Reserved
0
Reserved (default value)
0
One burst clock cycle (default value)
(4)
Y-Latency
1
Two burst clock cycles
R valid Low during valid burst clock edge (default
0
value)
1
R valid Low 1 data cycle before valid burst clock edge
0
Interleaved (default value)
Burst type
1
Sequential
0
Falling burst clock edge (default value)
1
Rising burst clock edge
00
Reserved (default value)
01
Reserved
10
Reserved
11
Reserved
0
Wrap (default value)
Wrapping
1
No wrap
000
Reserved (default value)
001
4 double-words
010
8 double-words
011
Reserved
Burst length
100
Reserved
101
Reserved
110
Reserved
111
Continuous
– t
+ t
AVQV
LLKH
QVKH
is the clock period and t
K
SYSTEM MARGIN
+ t
KHQV
SYSTEM MARGIN
Bus operations
Description
(2)
) + t
< (X -1) t
. (X is an integer
SYSTEM MARGIN
K
is the time margin required for the
+ t
< Y t
QVKH
K.
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