M58BW016DB80T3F

Manufacturer Part NumberM58BW016DB80T3F
ManufacturerMicron Technology Inc
M58BW016DB80T3F datasheet
 


Specifications of M58BW016DB80T3F

Lead Free Status / Rohs StatusNot Compliant  
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Page 16/70

Download datasheet (2Mb)Embed
PrevNext
Signal descriptions
2.9
Burst Clock (K)
The Burst Clock, K, is used to synchronize the memory with the external bus during
synchronous burst read operations. Bus signals are latched on the active edge of the Clock.
The Clock can be configured to have an active rising or falling edge. In synchronous burst
read mode the address is latched on the first active clock edge when Latch Enable is Low,
V
, or on the rising edge of Latch Enable, whichever occurs first.
IL
During asynchronous bus operations the Clock is not used.
2.10
Burst Address Advance (B)
The Burst Address Advance, B, controls the advancing of the address by the internal
address counter during synchronous burst read operations.
Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the
X-latency time has expired. If Burst Address Advance is Low, V
counter advances. If Burst Address Advance is High, V
not change; the same data remains on the data inputs/outputs and Burst Address Advance
is not sampled until the Y-latency expires.
The Burst Address Advance, B, may be tied to V
2.11
Valid Data Ready (R)
The Valid Data Ready output, R, is an open drain output that can be used, during
synchronous burst read operations, to identify if the memory is ready to output data or not.
The Valid Data Ready output can be configured to be active on the clock edge of the invalid
data read cycle or one cycle before. Valid Data Ready, at V
will be available. When Valid Data Ready is Low, V
active.
In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other
components with the same Valid Data Ready signal to create a unique system Ready
signal. The Valid Data Ready output has an internal pull-up resistor of around 1 M powered
from V
, designers should use an external pull-up resistor of the correct value to meet the
DDQ
external timing requirements for Valid Data Ready going to V
2.12
Write Protect (WP)
The Write Protect, WP, provides protection against program or erase operations. When
Write Protect, WP, is at V
configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at
V
all the blocks can be programmed or erased, if no other protection is used.
IH
2.13
Supply voltage (V
The supply voltage, V
the V
pin, including the program/erase controller.
DD
16/70
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
.
IL
IL
the first two (in the bottom configuration) or last two (in the top
IL
)
DD
, is the core power supply. All internal circuits draw their current from
DD
, the internal address
IL
, the internal address counter does
IH
, indicates that new data is or
IH
, the previous data outputs remain
.
IH