MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 121

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

3.3.2.9
Read: Anytime
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see device overview chapter.
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
as defined in
without using the address bus.
Freescale Semiconductor
Module Base + 0x0030
Starting address location affected by INITRG register setting.
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
Reset
actual reset state of this register.
PIX[5:0]
Field
5:0
W
R
1
Table
Program Page Index Register (PPAGE)
—
0
Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM
array pages is to be accessed in the program page window as shown in
7
Normal writes to this register take one cycle to go into effect. Writes to this
register using the special access of the CALL and RTC instructions will be
complete before the end of the associated instruction.
3-14. CALL and RTC instructions have special access to read and write this register
= Unimplemented or Reserved
—
0
6
Figure 3-11. Program Page Index Register (PPAGE)
Table 3-13. MEMSIZ0 Field Descriptions
MC9S12C-Family / MC9S12GC-Family
PIX5
—
5
Rev 01.24
PIX4
NOTE
—
4
Description
Chapter 3 Module Mapping Control (MMCV4) Block Description
PIX3
—
3
PIX2
Table
—
2
3-14.
PIX1
—
1
PIX0
—
0
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