MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 319

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Module Base + 0x00X1
Module Base + 0x00X2
ID[2:0]
Field
RTR
IDE
7:5
4
3
Reset:
Reset:
W
W
R
R
Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number. See also ID bits in
Remote Transmission Request — This flag reflects the status of the Remote Transmission Request bit in the
CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the
transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of
the RTR bit to be sent.
0 Data frame
1 Remote frame
ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In
the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.
0 Standard format (11 bit)
1 Extended format (29 bit)
ID2
7
x
7
x
Figure 10-30. Identifier Register 1 — Standard Mapping
Figure 10-31. Identifier Register 2 — Standard Mapping
= Unused; always read ‘x’
= Unused; always read ‘x’
ID1
6
x
6
x
Table 10-29. IDR1 Register Field Descriptions
MC9S12C-Family / MC9S12GC-Family
ID0
5
x
5
x
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
RTR
4
x
4
x
Description
IDE (=0)
x
x
3
3
2
x
2
x
Table
10-28.
x
x
1
1
0
x
0
x
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