MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 264

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.3.2.9
This register controls the COP (computer operating properly) watchdog.
Read: anytime
Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode
Write: RSBCK: once
264
Module Base + 0x0008
RSBCK
CR[2:0]
Reset
WCOP
Field
2:0
7
6
W
R
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the time-
out logic restarts and the user must wait until the next window before writing to ARMCOP.
exact duration of this window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in active BDM mode.
1 Stops the COP and RTI counters whenever the part is in active BDM mode.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP
counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by
periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
CRG COP Control Register (COPCTL)
0
7
= Unimplemented or Reserved
1. OSCCLK cycles are referenced from the previous COP time-out reset
RSBCK
(writing 0x0055/0x00AA to the ARMCOP register)
CR2
0
6
0
0
0
0
1
1
1
1
Figure 9-12. CRG COP Control Register (COPCTL)
Table 9-8. COPCTL Field Descriptions
CR1
0
0
1
1
0
0
1
1
Table 9-9. COP Watchdog Rates
MC9S12C-Family / MC9S12GC-Family
0
0
5
CR0
0
1
0
1
0
1
0
1
Rev 01.24
0
0
4
Description
Cycles to Time Out
COP disabled
OSCCLK
0
0
3
2
2
2
2
2
2
2
14
16
18
20
22
23
24
(1)
CR2
0
2
Table
Freescale Semiconductor
CR1
0
1
Table 9-9
9-9). The COP time-
shows the
CR0
0
0