MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 245

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.4
The ATD10B8C is structured in an analog and a digital sub-block.
8.4.1
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies V
8.4.1.1
The sample and hold (S/H) machine accepts analog signals from the external surroundings and stores them
as capacitor charge on a storage node.
The sample process uses a two stage approach. During the first stage, the sample amplifier is used to
quickly charge the storage node.The second stage connects the input directly to the storage node to
complete the sample for high accuracy.
When not sampling, the sample and hold machine disables its own clocks. The analog electronics still draw
their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the
analog power consumption.
The input analog signals are unipolar and must fall within the potential range of V
8.4.1.2
The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold
machine.
8.4.1.3
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly
charged to the sample potential.
8.4.1.4
The A/D machine performs analog-to-digital conversions. The resolution is program selectable at either 8
or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the
stored analog sample potential with a series of digitally generated analog potentials. By following a binary
search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled
potential.
When not converting the A/D machine disables its own clocks. The analog electronics still draws quiescent
current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power
consumption.
Only analog input signals within the potential range of V
in a non-railed digital output codes.
Freescale Semiconductor
Functional Description
Analog Sub-block
Sample and Hold Machine
Analog Input Multiplexer
Sample Buffer Amplifier
Analog-to-Digital (A/D) Machine
DDA
and V
SSA
allow to isolate noise of other MCU circuitry from the analog sub-block.
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
RL
to V
RH
(A/D reference potentials) will result
SSA
to V
DDA
.
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