MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 429

MC9S12C128VFU

Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC9S12C128VFU

Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

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14.4.4
Baud rate generation consists of a series of divider stages. Six bits in the SPI Baud Rate register (SPPR2,
SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in
the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits
(SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor
equation is shown in
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection
bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor
becomes 4. When the selection bits are 010, the module clock divisor becomes 8 etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When
the preselection bits are 010, the divisor is multiplied by 3, etc. See
for all bit conditions, based on a 25-MHz bus clock. The two sets of selects allows the clock to be divided
by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
Freescale Semiconductor
End of Idle State
SCK Edge Nr.
MSB first (LSBFE = 0):
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
MOSI pin
MISO pin
LSB first (LSBFE = 1):
L
T
I
= Minimum idling time between transfers (minimum SS high time), not required for back to back transfers
= Minimum leading time before the first SCK edge, not required for back to back transfers
= Minimum trailing time after the last SCK edge
SPI Baud Rate Generation
Figure 14-11
tL
1
MSB
LSB
2
Figure 14-10. SPI Clock Format 1 (CPHA = 1)
3
Begin
Bit 6
Bit 1
4
MC9S12C-Family / MC9S12GC-Family
5
Bit 5
Bit 2
6
7
Rev 01.24
Bit 4
Bit 3
8
Transfer
9
Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
Bit 3
Bit 4
10
11
Bit 2
Bit 5
12
Table 14-7
13 14
Bit 1
Bit 6
End
15
MSB
LSB
for baud rate calculations
16
tT
Minimum 1/2 SCK
Begin of Idle State
tI
for t
T
tL
, t
l
, t
L
429

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