MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 366

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
Reference
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
366
Module Base + 0x0012
Module Base + 0x0013
Module Base + 0x0014
Reset
Reset
Reset
•
•
•
•
W
W
W
R
R
R
The channel is disabled
Left aligned output (CAEx = 0)
PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)
PWMx period = channel clock period * (2 * PWMPERx)
Section 12.4.2.3, “PWM Period and Duty,”
Bit 7
Bit 7
Bit 7
0
0
0
7
7
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 12-21. PWM Channel Period Registers (PWMPER0)
Figure 12-22. PWM Channel Period Registers (PWMPER1)
Figure 12-23. PWM Channel Period Registers (PWMPER2)
6
0
6
0
6
0
6
6
6
MC9S12C-Family / MC9S12GC-Family
5
0
5
0
5
0
5
5
5
Rev 01.24
NOTE
4
0
4
0
4
0
4
4
4
for more information.
Section 12.4.2.8, “PWM Boundary Cases.”
3
0
3
0
3
0
3
3
3
2
0
2
0
2
0
2
2
2
Freescale Semiconductor
1
0
1
0
1
0
1
1
1
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0