MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 418

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
14.3.2.2
Read: anytime
Write: anytime; writes to the reserved bits have no effect
418
Module Base 0x0001
MODFEN
BIDIROE
SPISWAI
Reset
SPC0
Field
4
3
1
0
W
R
Bidirectional
Pin Mode
Normal
Normal
Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration refer to
force the SPI system into idle state.
0 SS port pin is not used by the SPI
1 SS port pin with MODF feature
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled
1 Output buffer enabled
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode
1 Stop SPI clock generation when in wait mode
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
SPI Control Register 2 (SPICR2)
0
0
7
= Unimplemented or Reserved
0
0
6
SPC0
0
1
0
Table
Figure 14-4. SPI Control Register 2 (SPICR2)
Table 14-5. Bidirectional Pin Configurations
Table 14-4. SPICR2 Field Descriptions
14-3. In master mode, a change of this bit will abort a transmission in progress and
MC9S12C-Family / MC9S12GC-Family
BIDIROE
0
0
5
X
0
1
X
Master Mode of Operation
Slave Mode of Operation
MODFEN
Rev 01.24
MISO not used by SPI
0
4
Description
Slave Out
Master In
MISO
BIDIROE
0
3
0
0
2
Master Out
Master I/O
Master In
Slave In
MOSI
SPISWAI
Freescale Semiconductor
Table
0
1
14-5. In master
SPC0
0
0