HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 192

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HD6417709SF100B

Manufacturer Part Number
HD6417709SF100B
Description
MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD6417709SF100B

Package
208LQFP
Family Name
SuperH
Maximum Speed
100 MHz
Operating Supply Voltage
1.7|3.3 V
Data Bus Width
32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
96
Interface Type
IrDA/SCI/SCIF/UDI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Operating Temperature
-20 to 75 °C
Number Of Timers
3

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Table 6.8
Item
Time for priority
decision and SR
mask bit comparison
Wait time until end
of sequence being
executed by CPU
Time from interrupt
exception handling
(save of SR and PC)
until fetch of first
instruction of
exception handler is
started
Rev. 5.00, 09/03, page 146 of 760
Interrupt Response Time
NMI
0.5
+ 0.5
+ 0.5
X ( 0)
5
Icyc
Icyc
Bcyc
Pcyc
Icyc X ( 0)
IRQ
0.5
+ 1
+ 4.5
Pcyc *
5
Icyc
Number of States
Icyc
Bcyc
4
Icyc X ( 0)
PINT
0.5
+ 3.5
5
Icyc
Icyc
Pcyc
Icyc X ( 0)
Peripheral
Modules
0.5
+ 1.5
Pcyc *
0.5
+ 3
5
Icyc
Icyc
Icyc
Pcyc *
5
Icyc Interrupt exception
6
Notes
handling is kept
waiting until the
executing instruc-
tion ends. If the
number of instruc-
tion execution
states is S *
maximum wait
time is: X = S – 1.
However, if BL is
set to 1 by instru-
ction execution or
by an exception,
interrupt exception
handling is
deferred until
completion of an
instruction that
clears BL to 0. If
the following
instruction masks
interrupt exception
handling, the
handling may be
further deferred.
1
, the

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