HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 361

no-image

HD6417709SF100B

Manufacturer Part Number
HD6417709SF100B
Description
MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD6417709SF100B

Package
208LQFP
Family Name
SuperH
Maximum Speed
100 MHz
Operating Supply Voltage
1.7|3.3 V
Data Bus Width
32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
96
Interface Type
IrDA/SCI/SCIF/UDI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Operating Temperature
-20 to 75 °C
Number Of Timers
3

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417709SF100B
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
HD6417709SF100BV
Manufacturer:
HITACHI
Quantity:
12 388
Part Number:
HD6417709SF100BV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
I/O Card Interface Timing: Figures 10.37 and 10.38 show the timing for the PCMCIA I/O card
interface.
Switching between the I/O card interface and the IC memory card interface is performed
according to the accessed address. When PCMCIA is designed for physical space area 5, the bus
access is automatically performed as an I/O card interface access when a physical address from
H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6,
the bus access is automatically performed as an I/O card interface access when a physical address
from H'1A000000 to H'1BFFFFFF is accessed.
When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area
in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU.
When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic
sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for are
5 or area 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is
recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the
I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits.
Figure 10.39 shows the basic timing for dynamic bus sizing.
In big-endian mode, the IOIS16 signal is not supported, and should be fixed low.
Rev. 5.00, 09/03, page 315 of 760

Related parts for HD6417709SF100B