HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 583

• Manufacturer Part Number: HD6417709SF100B
• Description: MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of HD6417709SF100B

• Package: 208LQFP
• Family Name: SuperH
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 1.7|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 96
• Interface Type: IrDA/SCI/SCIF/UDI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Operating Temperature: -20 to 75 °C
• Number Of Timers: 3

16.3
16.3.1
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually. Refer to section 14.3.2, Operation in Asynchronous Mode. The SCIF
has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the
CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals
as modem control signals. The transmission format is selected in the serial mode register
(SCSMR), as shown in table 16.7. The SCIF clock source is selected by the combination of the
CKE1 and CKE0 bits in the serial control register (SCSCR), as shown in table 16.8.
Table 16.7 SCSMR Settings and SCIF Communication Formats
Mode
Asynchronous
Data length is selectable: 7 or 8 bits.
Parity and multiprocessor bits are selectable, as is the stop bit length (1 or 2 bits). The
combination of the preceding selections constitutes the communication format and character
length.
In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO
data full, receive data ready, and breaks.
In transmitting, it is possible to detect transmit FIFO data empty.
The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
An internal or external clock can be selected as the SCIF clock source.
When an internal clock is selected, the SCIF operates using the on-chip baud rate
generator, and can output a serial clock signal with a frequency 16 times the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
Operation
Overview
Bit 6
CHR
0
1
Bit 5
PE
0
1
0
1
SCSMR Settings
Bit 3
STOP
0
1
0
1
0
1
0
1
Data
Length
8-bit
7-bit
Parity
Bit
Not set
Set
Not set
Set
SCIF Communication Format
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
Rev. 5.00, 09/03, page 537 of 760