HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 422

• Manufacturer Part Number: HD6417709SF100B
• Description: MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of HD6417709SF100B

• Package: 208LQFP
• Family Name: SuperH
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 1.7|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 96
• Interface Type: IrDA/SCI/SCIF/UDI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Operating Temperature: -20 to 75 °C
• Number Of Timers: 3

11.4
11.4.1
The DMAC has an on-chip compare match timer (CMT) to generate DMA transfer requests. The
CMT has a 16-bit counter.
Features
The CMT has the following features:
Block Diagram
Figure 11.24 shows a block diagram of the CMT.
Rev. 5.00, 09/03, page 376 of 760
CMCOR0:
Four types of counter input clock can be selected
Generates a DMA transfer request when compare match occurs.
CMCSR0:
CMCNT0:
CMSTR:
One of four internal clocks (P /4, P /8, P /16, P /64) can be selected.
Compare Match Timer (CMT)
Overview
Compare match timer start register
Compare match timer control/status register 0
Compare match timer constant register 0
Compare match timer counter 0
Control circuit
Figure 11.24 Block Diagram of CMT
P /4 P /8 P /16 P /64
Module bus
Clock selection
Internal bus
interface
Bus
CMT