HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 420

• Manufacturer Part Number: HD6417709SF100B
• Description: MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
• Manufacturer: Renesas Electronics America

Specifications of HD6417709SF100B

• Package: 208LQFP
• Family Name: SuperH
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 1.7|3.3 V
• Data Bus Width: 32 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 96
• Interface Type: IrDA/SCI/SCIF/UDI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Operating Temperature: -20 to 75 °C
• Number Of Timers: 3

11.3.7
The DMA transfer ending conditions are different for ending on an individual channel and ending
on all channels together. At the end of transfer, the following conditions are applied except in the
case where the value set in the DMA transfer count register (DMATCR) reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto-request)
(b) Burst mode, edge detection (external request, internal request, and auto-request)
(c) Burst mode, level detection (external request)
(d) Bus timing when transfer is suspended
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit in the
channel’s CHCR register is cleared to 0.
Rev. 5.00, 09/03, page 374 of 760
When the transfer ending conditions are satisfied, DMAC transfer request acceptance is
suspended. The DMAC stops operating after completing the number of transfers that it has
accepted until the ending conditions are satisfied.
In cycle-steal mode, the operation is the same regardless of whether the transfer request is
detected by level or edge.
The timing from the point where the ending conditions are satisfied to the point where the
DMAC stops operating is the same as in cycle-steal mode. With edge detection in burst mode,
though only one transfer request is generated to start the DMAC, stop request sampling is
performed at the same timing as transfer request sampling in cycle-steal mode. As a result, the
period when a stop request is not sampled is regarded as the period when a transfer request is
generated, and after performing the DMA transfer for this period, the DMAC stops operating.
Same as in (a).
Transfer is suspended when one transfer ends. Even if transfer ending conditions are satisfied
during a read in direct address transfer in dual address mode, the subsequent write process is
executed, and after the transfer in (a) to (c) above has been executed, DMAC operation is
suspended.
When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in CHCR. If the IE (interrupt enable)
bit has been set, a DMAC interrupt (DEI) request is sent to the CPU. This transfer ending does
not apply to (a) to (d) described above.
When DE in CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR register. The TE bit is not set when this happens. This transfer ending applies
to (a) to (d) described above.
DMA Transfer Ending Conditions