HD6417709SF100B Renesas Electronics America, HD6417709SF100B Datasheet - Page 675

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HD6417709SF100B

Manufacturer Part Number
HD6417709SF100B
Description
MCU 32-Bit SuperH RISC ROMLess 1.7V/3.3V 208-Pin LQFP
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD6417709SF100B

Package
208LQFP
Family Name
SuperH
Maximum Speed
100 MHz
Operating Supply Voltage
1.7|3.3 V
Data Bus Width
32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
96
Interface Type
IrDA/SCI/SCIF/UDI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Operating Temperature
-20 to 75 °C
Number Of Timers
3

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20.4.4
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t
conversion timing. Table 20.4 indicates the A/D conversion time.
As indicated in figure 20.6, the A/D conversion time includes t
length of t
time therefore varies within the ranges indicated in table 20.4.
In multi mode and scan mode, the conversion time values given in table 20.4 apply to the first
conversion. In the second and subsequent conversions, the conversion time is fixed at 512 states
when CKS = 0 in ADCSR, or 256 states when CKS = 1. In both cases, the CKS bit should be set
according to the P frequency so that the conversion time is within the range shown in table 23.10
in section 23, Electrical Characteristics.
Input Sampling and A/D Conversion Time
Legend
t
t
t
Notes:
D
D
SPL
CONV
varies depending on the timing of the write access to ADCSR. The total conversion
D
after the ADST bit is set to 1, then starts conversion. Figure 20.6 shows the A/D
Input sampling
A/D conversion start delay
Input sampling time
A/D conversion time
1. ADCSR write cycle
2. ADCSR address
Address
timing
signal
Write
ADF
P
Figure 20.6 A/D Conversion Timing
*1
*2
t
D
t
SPL
t
CONV
D
and the input sampling time. The
Rev. 5.00, 09/03, page 629 of 760

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