STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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STM32F103xC, STM32F103xD, STM32F103xE
Table 75.
Document revision history
Date
Revision
21-Jul-2008
Document status promoted from Preliminary Data to full datasheet.
FSMC (flexible static memory controller) on page 15
Number of complementary channels corrected in
STM32F103xC, STM32F103xD and STM32F103xE performance line
block
diagram.
Power supply supervisor on page 17
Table 10: General operating conditions on page
Table notes revised in
Section 5: Electrical
Capacitance modified in
Figure 12: Power supply scheme on page
Table 52: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)
Table 53: SPI characteristics
SPI timing diagram - slave mode and CPHA = 0 on page
Minimum SDA and SCL fall time value for Fast mode removed from
3
Table 51: I2C characteristics on page
I
values and some I
DD_VBAT
to
Table 17: Typical and maximum current consumptions in Stop and
Standby modes on page
Table 30: Flash memory endurance and data retention on page 63
updated.
t
modified in
Table 53: SPI characteristics on page
su(NSS)
EO corrected in
Table 62: ADC accuracy on page
Typical connection diagram using the ADC on page 106
corrected.
Typical T
value removed from
S_temp
page
110.
Section 6.1: Package mechanical data on page 111
Small text changes.
Doc ID 14611 Rev 8
Revision history
Changes
modified.
Figure 1:
modified and V
added to
DDA
42.
characteristics.
modified, t
modified in
Figure 49:
h(NSS)
96.
93, note 1 modified.
values with regulator in run mode added
DD
48.
95.
105.
Figure 58:
and note below
Table 64: TS characteristics on
updated.
40.
updated.
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