STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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STM32F103xC, STM32F103xD, STM32F103xE
Table 31.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Symbol
t
FSMC_NEx low to FSMC_NADV low
v(NADV_NE)
t
FSMC_NADV low time
w(NADV)
1. C
= 15 pF.
L
2. Based on characterisation, not tested in production.
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
FSMC_NEx
FSMC_NOE
FSMC_NWE
FSMC_A[25:0]
FSMC_NBL[1:0]
FSMC_D[15:0]
FSMC_NADV
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 32.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
t
FSMC_NE low time
w(NE)
t
FSMC_NEx low to FSMC_NWE low
v(NWE_NE)
t
FSMC_NWE low time
w(NWE)
t
FSMC_NWE high to FSMC_NE high hold time
h(NE_NWE)
t
FSMC_NEx low to FSMC_A valid
v(A_NE)
t
Address hold time after FSMC_NWE high
h(A_NWE)
t
FSMC_NEx low to FSMC_BL valid
v(BL_NE)
t
FSMC_BL hold time after FSMC_NWE high
h(BL_NWE)
t
FSMC_NEx low to Data valid
v(Data_NE)
t
Data hold time after FSMC_NWE high
h(Data_NWE)
Parameter
t
w(NE)
t
v(NWE_NE)
t
v(A_NE)
Address
t
v(BL_NE)
NBL
t
v(Data_NE)
t
v(NADV_NE)
t
w(NADV)
(1)
Parameter
Doc ID 14611 Rev 8
Electrical characteristics
Min
Max
5
t
+ 1.5
HCLK
t
t
h(NE_NWE)
w(NWE)
t
h(A_NWE)
t
h(BL_NWE)
t
h(Data_NWE)
Data
Min
Max
3t
– 1
3t
+ 2
HCLK
HCLK
t
– 0.5
t
+ 1.5
HCLK
HCLK
t
– 0.5
t
+ 1.5
HCLK
HCLK
t
HCLK
7.5
t
HCLK
1.5
t
– 0.5
HCLK
t
+ 7
HCLK
t
HCLK
(1) (2)
Unit
ns
ns
ai14990
(1)(2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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