STM32F103ZC

Manufacturer Part NumberSTM32F103ZC
DescriptionMainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
ManufacturerSTMicroelectronics
STM32F103ZC datasheet
 

Specifications of STM32F103ZC

CoreARM 32-bit Cortex™-M3 CPUConversion Range0 to 3.6 V
Dma12-channel DMA controllerSupported Peripheralstimers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timera 24-bit downcounter  
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Page 66/130

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Electrical characteristics
Table 32.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
Symbol
t
FSMC_NEx low to FSMC_NADV low
v(NADV_NE)
t
FSMC_NADV low time
w(NADV)
1. C
= 15 pF.
L
2. Based on characterisation, not tested in production.
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
FSMC_NE
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_NADV
Table 33.
Asynchronous multiplexed PSRAM/NOR read timings
Symbol
t
FSMC_NE low time
w(NE)
t
FSMC_NEx low to FSMC_NOE low
v(NOE_NE)
t
FSMC_NOE low time
w(NOE)
t
FSMC_NOE high to FSMC_NE high hold time
h(NE_NOE)
t
FSMC_NEx low to FSMC_A valid
v(A_NE)
t
FSMC_NEx low to FSMC_NADV low
v(NADV_NE)
t
FSMC_NADV low time
w(NADV)
FSMC_AD (address) valid hold time after
t
h(AD_NADV)
FSMC_NADV high
t
Address hold time after FSMC_NOE high
h(A_NOE)
66/130
STM32F103xC, STM32F103xD, STM32F103xE
Parameter
t
w(NE)
t
v(NOE_NE)
t
w(NOE)
t
v(A_NE)
Address
t
v(BL_NE)
NBL
t
su(Data_NE)
t
t
v(A_NE)
su(Data_NOE)
Address
Data
t
t
h(AD_NADV)
v(NADV_NE)
t
w(NADV)
Parameter
7t
HCLK
3t
HCLK
4t
HCLK
–1
3
t
HCLK
t
HCLK
t
HCLK
Doc ID 14611 Rev 8
(1)(2)
Min
Max
Unit
5.5
ns
t
+ 1.5
ns
HCLK
t
h(NE_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
h(Data_NE)
t
h(Data_NOE)
ai14892b
(1)(2)
Min
Max
Unit
– 2
7t
+ 2
ns
HCLK
– 0.5
3t
+ 1.5
ns
HCLK
– 1
4t
+ 2
ns
HCLK
ns
0
ns
5
ns
–1.5
t
+ 1.5
ns
HCLK
ns
ns