MT29F8G08FABWP Micron Technology, Inc, MT29F8G08FABWP Datasheet - Page 17

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MT29F8G08FABWP

Manufacturer Part Number
MT29F8G08FABWP
Description
Manufacturer
Micron Technology, Inc
Datasheet

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Data Input
READs
09005aef818a56a7 pdf/ 09005aef81590bdd source
2gb_nand_m29b__2.fm - Rev. H 9/05 EN
RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only
two ADDRESS cycles are required. Refer to the command descriptions to determine the
addressing requirements for each command.
Data is written to the data register on the rising edge of WE# when:
• CE#, CLE, and ALE are LOW, and
• the device is not busy.
Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 35 on
page 46 for additional data input details.
After a READ command is sent to the memory device, data is transferred from the mem-
ory array to the data register in
register, it is clocked out of the part by RE# going LOW. See Figure 38 on page 47 for
detailed timing information.
The READ STATUS (70h) command or the R/B# signal can be used to determine when
the device is ready. See the STATUS READ command section on page 29 for details.
2, 4, and 8Gb x8/x16 Multiplexed NAND Flash Memory
17
t
R. Typically
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
R is 25µs. When data is available in the data
©2004 Micron Technology, Inc. All rights reserved.
Bus Operation

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