peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 125

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

2.7.9.9
The boot configuration register, BOOTCONF, is a memory mapped register at address
C001
bit
BOOTCONF
bit
BOOTCONF
* written as “don’t care”, read as ‘0’
EPM This bit indicates that the chip is in EPROM boot mode. It is set when BOOT strap
2.7.9.10
Following is the bootroutine which resides in the internal bootrom.
.FORMAT 10000,1000
.EQU IOPAGE
.EQU BOOTCONF
.EQU MEMCONF
.EQU TESTCONF
.EQU STATUS1
.EQU EMUMB
.EQU OcemTraceBuff
.EQU OCEMadd
.EQU Version
.EQU MONITOR
.EQU BOOTCONFadd
.EQU BR_CODE
.EQU OCMD
.EQU OBUSY
.EQU ODT0
.EQU MCMD
Semiconductor Group
H
pins are active, the DBG strap pin is inactive and the ROM strap is active on reset
negation. This bit can be read/write by the user. While EPM bit is set, every read
during MOVP instruction is done from the boot ROM instead of the program
space.
Boot Configuration Register (BOOTCONF)
The Bootroutine
7
15
EPM
*
0xc0
0x01
0x02
0x03
0xf7fe
0xf400
0x0010
0x45
0xd0c0
0x7c00
0x4180
0x50
0x51
0x52
0x40
6
14
*
*
5
13
; Memory mapped I/O page
; BOOTCONF register offset address
; MEMCONF register offset address
; TESTCONF register offset address
; OCEM STATUS1 register
; Emulation mail box address
; Ocem Trace Buffer length
; <<<< TEMPORARY NUMBER
; chip Version
; monitor address (31K-32K)
(IOPAGE<<8) | BOOTCONF
; Branch opcode
; OAK mail box command register
; OAK mail box busy bit
; OAK mail box data reg 0
; micro-processor mail box command
register
*
*
2-79
4
12
*
*
3
11
Functional Block Description
*
*
2
10
*
*
1
9
*
*
PEB 20560
0
8
2003-08
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*