peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 182

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Table 2-30 (cont’d)
Interrupt
Sources
Number
S3
S4
S5
S6
S7
S8
S9
S10
Note: The FSC and RTC interrupts sources are reset by Interrupt Acknowledge line
2.14
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device or a modem, and parallel-to-serial conversion on data characters
received from the CPU. The µP can read the complete status of the UART at any time
during the functional operation. Status information reported includes the type and
condition of the transfer operations being performed by the UART, as well as any error
condition (parity, overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator that is capable of dividing the
timing reference clock input by 1 to (2
the internal transmitter logic. Provisions have also been made to use this 16 × clock for
driving the receiver logic.
The UART features full modem-control capability and a processor-interrupt system.
Interrupts can be programmed to the user’s requirements, minimizing the computing
required for handling the communications link.
(IACK) when the appropriate Interrupt Vector is driven on the data bus. The other
interrupts are reset by reading from or writing to the appropriate register in the
interrupt source module.
Thus the FSC and RTC interrupts are not supported in the pending interrupt status
register. It is recommended to mask the FSC and RTC interrupts in the Interrupt
Mask Register, when working with the pending interrupt status (not using the
interrupt vector).
Both interrupts can be generated via the µP-Mailbox interrupt by the DSP software
as the DSP uses FSC interrupts internally. It may also count the FSC interrupts to
e.g. 1 ms and then send a message to the µP.
Universal Asynchronous Receiver/Transmitter (UART)
Interrupt
Status
IS3
IS4
IS5
IS6
IS7
−
IS9
−
Interrupt
Source
SIDEC1
SIDEC2
SIDEC3
OAK-Mail Box write access to OBUSY
GPIO Port
FSC
UART
RTC
16
– 1), and of producing a 16 × clock for driving
2-136
Reset Control for Bits in IGIS0 and IGID1
SIDEC1: ISTA, EXIR
SIDEC2: ISTA, EXIR
SIDEC3: ISTA, EXIR
read access VDATA
not available (see note below)
see Table 2-36 on page 149
not available (see note below)
Functional Block Description
PEB 20560
2003-08