peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 200

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.14.1.9
This 8-bit read/write register does not control the UART in any way. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
bit
SCR
2.14.2
When the RCVR FIFO and receiver interrupts are enabled (FEWO = 1, ERBFI = 1)
RCVR interrupts will occur as follows:
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts
will occur as follows:
a) The receive data available interrupt will be issued to the µP when the FIFO has
b) The IIR receive data available indication also occurs when the FIFO trigger level is
c) The receiver line status interrupt (IIR = 06), as before, has higher priority than the
d) The data ready bit (DR) is set as soon as a character is transferred from the shift
a) A FIFO time-out interrupt will occur, if the following conditions exist:
b) Character times are calculated by using the RCLK input for a clock signal (this
c) When a time-out interrupt has occurred it is cleared and the timer reset when the
d) When a time-out interrupt has not occurred the time-out timer is reset after a new
– at least one character is in the FIFO
– the most recent serial character received was longer than 4 continuous character
– the most recent µP read of the FIFO was longer than 4 continuous character
reached its programmed trigger level; it will be cleared as soon as the FIFO drops
below its programmed trigger level.
reached, and like the interrupt it is cleared when the FIFO drops below the trigger
level.
received data available (IIR = 04) interrupt.
register to the RCVR FIFO. It is reset when the FIFO is empty.
makes the delay proportional to the baudrate).
µP reads one character from the RCVR FIFO.
character is received or after the µP reads the RCVR FIFO.
times ago (if 2 stop bits are programmed the second one is included in this time
delay).
times ago.
This will cause a maximum character received to interrupt issued delay of
160 ms at 300 Baud with a 12-bit character.
Scratchpad Register (SCR)
FIFO Interrupt Mode Operation
7
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2-154
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Functional Block Description
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PEB 20560
0
2003-08
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