peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 14

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

List of Figures
Semiconductor Group
Figure 2-29 QUAT-S with SACCO-B for Single-Channel LT-T Application. . . . . . . 2-49
Figure 2-30 SACCO-B1 Multiplexers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Figure 2-31 PEDIU Connection to the ELICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
Figure 2-32 CHI Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Figure 2-33 FSCD Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Figure 2-34 External Data/Program Read Access . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Figure 2-35 External Data Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Figure 2-36 External Program Write Access Due to MOVD . . . . . . . . . . . . . . . . . . 2-66
Figure 2-37 External Boot ROM Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Figure 2-38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71
Figure 2-39 Example: Flow of B-Channels between ELIC1 and PEDIU . . . . . . . . . 2-89
Figure 2-40 Accesses to the PEDIU RAM (circular buffer) at two
Figure 2-41 Block Diagram of the PCM-DSP Interface Unit (PEDIU) . . . . . . . . . . . 2-92
Figure 2-42 Block Structure of Circular Buffer (PEDIU RAM) in Different
Figure 2-43 Connection between CB bit and Accesses to the Circular
Figure 2-44 The Connection between CB bit and Accesses to the Circular
Figure 2-45 DOC Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-119
Figure 2-46 PFS Signal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-121
Figure 2-47 PDC Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122
Figure 2-48 Priority Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131
Figure 2-49 Interrupt Cascading (Slave Mode) in Siemens/Intel Bus Mode . . . . . 2-133
Figure 2-50 Interrupt Cascading (Daisy Chaining) in Siemens/Intel Bus Mode . . 2-134
Figure 2-51 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-138
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Figure 4-1
Figure 4-2
Figure 5-1
Figure 5-2
Figure 5-3
Consecutive Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90
PEDIU Work Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96
Buffer Blocks in PEDIU work Mode 0, 1 or 2 . . . . . . . . . . . . . . . . . . . . 2-99
Buffer Blocks in PEDIU work Mode 3 or 4 . . . . . . . . . . . . . . . . . . . . . 2-100
ELIC
Switching Paths Inside the EPIC
Pre-Processed Channel Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Interrupt Driven Transmission Sequence (Flow Diagram) . . . . . . . . . . 3-11
Interrupt Driven Transmission Sequence Example . . . . . . . . . . . . . . . 3-12
DMA Driven Transmission Example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Interrupt Driven Reception Example . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
DMA-Driven Reception Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
DOC/ELIC
Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Timing Relation Between Internal and External Clock . . . . . . . . . . . . . 5-25
Position of the FSC-Signal for FC-Modes 3 and 6 . . . . . . . . . . . . . . . . 5-33
Position of the FSC-Signal for FC-Mode 6. . . . . . . . . . . . . . . . . . . . . . 5-33
®
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
®
Interfaces for Initialization Example . . . . . . . . . . . . . . . . . 3-23
I-12
®
-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
PEB 20560
2003-08
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