peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 211

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

PEB 20560
Operational Description
frames. The synchronous state is lost if one bad clock cycle is found. The
synchronization status (gained or lost) can be read from an internal register and each
status change generates an interrupt.
3.1.3.2
Configurable Interface
The EPIC-1 provides up to four ports consisting each of a data output (DD#) and a data
input (DU#) line. The output pins are called “Data Downstream” pins and the input pins
are called “Data Upstream” pins. These modes are especially suited to realize a
standard serial PCM-interface (PCM-highway) or to implement an IOM (ISDN-Oriented
Modular) interface. The IOM-interface generated by the EPIC-1 offers all the functionality
like C/I- and monitor channel handling required for operating all kinds of IOM compatible
layer-1 and codec devices.
Data is transmitted and received at normal TTL/CMOS-levels at the CFI. Tri-state or
open-drain output drivers can be selected. In case of open-drain drivers, external
pull-up resistors are required. Unassigned output time-slots may be switched to high
impedance or be programmed to transmit a defined idle value. The selection between
the states “high impedance” or “idle value” can be performed on a per time-slot basis.
The CFI-standby function switches all CFI-output lines to high impedance with a single
command. Internally the device still works normally, only the output drivers are switched
off.
The number of time-slots per 8-kHz frame is programmable from 2 to 128. In other
words, the CFI-data rate can range between 128 kbit/s up to 8.192 Mbit/s. Since the
overall switching capacity is limited to 128 time-slots per direction, the number of CFI-
ports also depends on the required number of time-slots: in case of 32 time-slots per
frame (2.048 Mbit/s) for example, four highways are available, in case of 128 time-slots
per frame (8.192 Mbit/s), only one highway is available. Usually, the number of bits per
8-kHz frame is an integer multiple of the number of time-slots per frame (1 time-slot =
8 bits).
The timing characteristics at the CFI (data rate, bit shift, etc.) can be varied in a wide
range, but they are the same for each of the four CFI-ports, i.e. if a data rate of
2.048 Mbit/s is selected, all four ports run at this data rate of 2.048 Mbit/s. It is thus not
possible to have one port used in IOM-2 line card mode (2.048 Mbit/s) while another port
is used in IOM-2 terminal mode (768 kbit/s)!
Note: The integrated PCM-DSP interface unit (PEDIV) works correctly only at
2.048 Mbit/s or 4.096 Mbit/s data rate.
The clock and framing signals necessary to operate the configurable interface may be
derived either from the clock and framing signals of the PCM-interface (PDC and PFS
pins), or may be fed in directly via the DCL- and FSC-pins.
In the first case, the CFI-data rate is obtained by internally dividing down the PCM-clock
signal PDC. Several prescaler factors are available to obtain the most commonly used
Semiconductor Group
3-5
2003-08