peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 193

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

BI
THRE
TEMT
EIRF
Semiconductor Group
This bit is the Break Interrupt indicator. Bit 4 is set to a logic 1
whenever the received data input is held in the spacing (logic 0) state
for longer than a full word transmission time (that is, the total time of
start bit + data bits + parity + stop bits). The Bl indicator is reset
whenever the µP reads the contents of the line status register. In the
FIFO mode this error is associated with the particular character in the
FIFO it applies to. This error is revealed to the µP when its associated
character is at the top of the FIFO. When break occurs only one zero
character is loaded into the FIFO. The next character transfer is
enabled after SIN goes to the marking state and receives the next
valid start bit.
Note: Bits 1 through 4 are the error conditions that produce a
This bit is the Transmitter Holding Register Empty indicator. Bit 5
indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an
interrupt to the µP when the transmit holding register empty interrupt
enable is set high. The THRE bit is set to a logic 1 when a character
is transferred from the transmitter holding register into the transmitter
shift register. The bit is reset to logic 0 concurrently with the loading
of the transmitter holding register by the CPU. In the FIFO mode this
bit is set when the XMIT FIFO is empty; it is cleared when at least 1
byte is written to the XMIT FIFO.
This bit is the Transmitter Empty indicator. Bit 6 is set to a logic 1
whenever the transmitter holding register (THR) and the transmitter
shift register (TSR) are both empty. It is reset to a logic 0 whenever
either the THR or TSR contains a data character. In the FIFO mode
this bit is set to one whenever the transmitter FIFO and shift register
are both empty.
In the 16450 mode this is a 0. In the FIFO mode EIRF is set when
there is at least one parity error, framing error or break indication in
the FIFO. EIRF is cleared when the µP reads the LSR, if there are no
subsequent errors in the FIFO.
Note: The line status register is intended for read operations only.
receiver
corresponding conditions are detected and the interrupt is
enabled.
Writing to this register is not recommended as this operation is
only used for factory testing.
line
2-147
status
interrupt
Functional Block Description
whenever
any
PEB 20560
of
2003-08
the