peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 171

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

2.12.3
2.12.3.1
Address: 360
µP interface mode: read/write
Reset Value: 0001_00xx - where xx depends on input pins.
Note: bits 1…0 are read only Bits 7…5 are unused, and are read as ‘0’.
This register fulfils the following functions:
• DSP frequency indication.
• PCM Data Clock (PDC) frequency selection.
• Definition if the DOC functions as PCM clocks master (PDC and PFS generator)
DSPF1…0
Note: These bits are read only, and there value is determined by the input pins:
PDCF1…0
MS
Note: After reset, PDC/PFS are internally by the clocks generator, but the PDC/PFS pins
Semiconductor Group
bit 7
or as PCM clocks slave (the DOC gets PDC and PFS, as inputs).
0
FRQ1…0.
stay in tri-state. PDC/PFS are driven by the DOC, only after the first write access
to CCSEL0, if the DOC was configured as master.
Clocks Generator Registers Description
Clocks Select 0 Register (CCSEL0)
H
DSP frequency
00: 20 MHz
01: 30 MHz
10: 40 MHz
11: 61 MHz (used only for testing)
PDC frequency for ELIC0 and ELIC1
00: 8.192 MHz
01: 4.096 MHz
10: 2.048 MHz
11: reserved
Master/Slave (PDC & PFS internal/external)
0:
1:
0
slave - PDC and PFS are external.
master - PDC and PFS are internal and driven on IO
0
MS
2-125
PDCF1
Functional Block Description
PDCF0
DSPF1
PEB 20560
bit 0
DSPF0
2003-08