peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 198

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
bit
MCR
DTR
RTS
OUT1
OUT2
LOOP
Bits 5 through 7 These bits are permanently set to logic 0.
Details on each bit follow:
7
0
This bit controls the data terminal ready output. When bit 0 is set to
a logic 1, the DTR output is forced to a logic 0. When bit 0 is reset to
a logic 0, the DTR output is forced to a logic 1.
Note: The DTR output of the UART may be applied to an EIA
This bit controls the request to send output. Bit 1 affects the RTS
output in a manner identical to that described above for bit 0.
This bit controls the output 1 signal, which is an auxiliary user-
designated output. Bit 2 affects the OUT1 output in a manner
identical to that described above for bit 0.
This bit controls the output 2 signal, which is an auxiliary
user-designated output. Bit 3 affects the OUT2 output in a manner
identical to that described above for bit 0.
This bit provides a local loopback feature for diagnostic testing of the
UART. When bit 4 is set to logic 1, the following occurs: the
transmitter serial output (SOUT) is set to the marking (logic 1) state;
the receiver serial input (SIN) is disconnected; the output of the
transmitter shift register is ‘looped back’ into the receiver shift register
input; the four modem control inputs (CTS, DSR, Rl, and DCD) are
disconnected; and the four modem control outputs (DTR, RTS,
OUT1, and OUT2) are internally connected to the four modem control
inputs. The modem control output pins are forced to their inactive
state (high). In the diagnostic mode, data that is transmitted is
immediately received. This feature allows the processor to verify the
transmit and received data paths of the UART. In the diagnostic
mode, the receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the interrupt’s
sources are now the lower four bits of the modem control register
instead of the four modem control inputs. The interrupts are still
controlled by the interrupt enable register.
6
inverting line driver (such as the 1488) to obtain the proper
polarity input at the succeeding modem or data set.
0
5
0
4
2-152
LOOP0
3
OUT2
Functional Block Description
2
OUT1
1
RTS
PEB 20560
0
2003-08
DTR