peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 206

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Siemens provides for the DOC upon request a Boundary Scan Description Language,
so called DSDL File.
2.17
During DOC HW reset:
• All signal lines with input/output (I/O) capability are switched to input direction.
• The state of each output pin is as defined in the pin description tables (Table 1-1 to
• The integrated clock generator provides the necessary clocks to both ELICs.
• PDC2, PDC4, PDC8, PFS, DCL and FSC are driven internally, but these I/O pins are
• The OAK clock frequency is defined according to FRQ1…0 input pins.
• CLK 61.44 MHz must be provided to the DOC via CLK61 input pin.
• CLK30, CLK15 and CLK7 are driven by the DOC, as usual
• All the registers get the reset value, that defined in the register overview, section 5.
Table 1-7).
Both ELICs PDC and DCL are driven by the internal PDC8 (= CLK16 div. by 2).
Both ELICs PFS and FSC are driven by the internal PFS (= CLK16 div. by 2048).
not driven by the DOC, and stay in tri-state. PDC2, PDC4, PDC8 and PFS starts to be
driven by the DOC after the first write access to CCSEL0, and only if the DOC were
configured as MASTER. DCL and FSC starts to be driven by the DOC after the first
write access to CCSEL1, and only if these signals were configured as outputs.
If FRQ1…0 pins are ‘10’ (OAK clock frequency = 40 MHz), then a 40 MHz crystal must
be connected to pins CLK40-XI and CLK40-XO.
Reset Logic
2-160
Functional Block Description
PEB 20560
2003-08