peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 302

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

RFO
RFS
5.1.1.5.6
Access: write
Reset value: 00
Note: The maximum time between writing to the CMDR-register and the execution of the
RMC
RHR
XREP
Semiconductor Group
bit 7
RMC
command is 2.5 HDC-clock cycles. Therefore, if the CPU operates with a very high
clock speed in comparison to the SACCO-clock, it is recommended that the bit
STAR:CEC is checked before writing to the CMDR-register to avoid loosing of
commands.
Command Register (CMDR)
Receive Frame Overflow.
A frame could not be stored due to the occupied RFIFO (i.e. whole frame has
been lost). This interrupt can be used for statistical purposes and indicates,
that the CPU does not respond quickly enough to an incoming RPF- or RME-
interrupt.
Receive Frame Start.
This is an early receiver interrupt activated after the start of a valid frame has
been detected, i.e. after a valid address check in operation modes providing
address recognition, otherwise after the opening flag (transparent mode 0),
delayed by two bytes.
After a RFS-interrupt the contents of
are valid and can by read by the CPU.
The RFS-interrupt is maskable by programming bit CCR2:RIE.
Receive Message Complete.
A ‘1’ confirms, that the actual frame or data block has been fetched following
a RPF- or RME-interrupt, thus the occupied space in the RFIFO can be
released.
Reset HDLC-Receiver.
A ‘1’ deletes all data in the RFIFO and in the HDLC-receiver.
Extended transparent mode 0,1: XREP
Together with XTF- and XME-set (CMDR = 2A
transmits the contents of the XFIFO (1…32 bytes) fully transparent without
HDLC-framing, i.e. without flag, CRC-insertion, bit stuffing.
• RHCR
• RAL1
• RSTA bit3-0
RHR
H
XREP
0
5-59
XPD/
XTF
XDD
H
Description of Registers
) the SACCO repeatedly
XME
PEB 20560
bit 0
XRES
2003-08