am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 34

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

1-376
Polling
When there is no channel activity and there is no pre- or
post-receive or transmit activity being performed by the
PCnet-ISA controller, then the PCnet-ISA controller will
periodically poll the current receive and transmit de-
scriptor entries in order to ascertain their ownership. If
the DPOLL bit in CSR4 is set, then the transmit polling
function is disabled.
A typical polling operation consists of the following: The
PCnet-ISA controller will use the current receive de-
scriptor address stored internally to vector to the
appropriate Receive Descriptor Table Entry (RDTE). It
AMD
RES
RLEN RES
TLEN RES
CSR2
IADR[23:16]
Initialization
LADRF[31:16]
LADRF[47:32]
LADRF[63:48]
LADRF[15:0]
PADR[15:0]
24-Bit Base Address
PADR[31:16]
PADR[47:32]
RDRA[15:0]
TDRA[15:0]
Initialization Block
MODE
Block
Pointer to
RDRA[23:16]
TDRA[23:16]
Initialization Block and Descriptor Rings
IADR[15:0]
CSR1
P R E L I M I N A R Y
16907B-7
Buffers
Buffers
Am79C960
RCV
XMT
1st desc.
start
RMD0
1st desc.
start
TMD0
RX DESCRIPTOR RINGS
will then use the current transmit descriptor address
(stored internally) to vector to the appropriate Transmit
Descriptor Table Entry (TDTE). These accesses will be
made to RMD1 and RMD0 of the current RDTE and
TMD1 and TMD0 of the current TDTE at periodic polling
intervals. All information collected during polling activity
will be stored internally in the appropriate CSRs. (i.e.
CSR18–19, CSR20–21, CSR40, CSR42, CSR50,
CSR52). UnOWNed descriptor status will be internally
ignored.
RX DESCRIPTOR RINGS
RX DESCRIPTOR RINGS
Buffer
Buffer
Data
Data
1
1
RMD1 RMD2 RMD3
N
TMD1 TMD2 TMD3
RCV Descriptor
M
XMT Descriptor
Ring
Ring
Buffer
Buffer
N
Data
Data
2
2
M
N
M
2nd desc.
start
2nd desc.
start
RMD0
N
TMD0
M
•
Buffer
Buffer
Data
Data
•
•
N
M
•
•
•
16907B-7