am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 74

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

15-5
4
3
2-0
ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port (RAP). The table below defines the ISACSRs which
can be accessed. All registers are 16 bits. The “Default”
value is the value in the register after reset and is
hexadecimal.
ISACSR0: Master Mode Read Active
Bit
15-4
3-0
1-416
ISACSR
0
1
2
3
4
5
6
7
AMD
GPSIEN
MSRDA
Name
RES
RPA
RES
RES
MNEMONIC
MSRDA
MSWRA
MC
Reserved
LED0
LED1
LED2
LED3
Reserved locations. Written as
zero and read as undefined.
This mode places the PCnet-ISA
controller in the GPSI Mode. This
mode will reconfigure the Exter-
nal Address Pins so that the
GPSI port is exposed. This al-
lows bypassing the MENDEC-
TMAU logic. This bit should only
be set if the external logic sup-
ports GPSI operation. Damage
to the device may occur in a non-
GPSI configuration. Refer to the
GPSI section.
Runt Packet Accept. This bit
forces the CORE receive logic to
accept Runt Packets. This bit al-
lows for faster testing.
For test purposes only. Reserved
locations. Written as zero and
read as undefined.
Reserved locations. Written as
zero and read as undefined.
This register is used to tune the
MEMR command signal active
time. The value stored in MSRDA
defines the number of 50 ns peri-
ods that the command signal is
Default
0005H
0005H
0002H
N/A
0000H
0084H
0008H
0090H
Description
Master Mode
Read Active
Master Mode
Write Active
Miscellaneous
Configuration
Reserved for
future AMD use
Link Integrity
Default: RCV
Default: RCVPOL
Default: XMT
Name
P R E L I M I N A R Y
Am79C960
ISACSR1: Master Mode Write Active
Bit
15-4
3-0
ISACSR2: Miscellaneous Configuration
Bit
15 MODE_STATUS Mode Status. This is a read-only
14-8
7
6-5
4
EISA_LVL
ISAINACT
MSWRA
Name
Name
RES
RES
RES
active. The default value of 5h in-
dicates 250 ns pulse widths. A
value of 0 or 1 will generate 50 ns
wide commands.
Reserved locations. Written as
zero and read as undefined.
This register is used to tune the
MEMW command signal active
time.
MSWRA defines the number of
50 ns periods that the command
signal is active. The default value
of 5h indicates 250 ns pulse
widths. A value of 0 or 1 will gen-
erate 50 ns wide commands.
register which indicates whether
the PCnet-ISA is configured in
shared memory mode.
condition
memory while a clear condition
indicates bus-master condition.
Reserved locations. Written and
read as zero.
EISA_LVL allows for EISA level-
sensitive
EISA_LVL
RESET
EISA_LVL is a zero, the IRQ pin
is configured for ISA edge sensi-
tive full CMOS driver. When
EISA_LVL is set by writing a one,
the IRQ pin is configured as an
EISA level-sensitive interrupt
open
EISA_LVL is set to one, the IRQ
pin assertion level is active low.
Reserved locations. Written and
read as zero.
ISAINACT allows for reduced in-
active timing appropriate for
modern
ISAINACT
RESET
ISAINACT is a zero, tMMR3 and
tMMW3 parameters are nomi-
nally 200 ns, which is com-
patible with EISA system. When
ISAINACT is set by writing a one,
The
drain
is
is
Description
Description
indicates
interrupt
is
is
ISA
value
asserted.
asserted.
output.
cleared
cleared
stored
machines.
support.
shared-
When
When
When
A set
when
when
in