am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 66

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

2
1
0
CSR16: Initialization Block Address Lower
Bit
15-0
1-408
LOOP
0
1
1
1
AMD
LOOP
Name
IADR
DRX
DTX
INTL
X
0
1
1
MENDECL
X
X
0
1
In loopback mode, this bit deter-
mines if the transmitter appends
FCS or if the receiver checks the
FCS.
This bit was called DTCR in the
LANCE (Am7990).
Read/write accessible only when
STOP bit is set.
Loopback
PCnet-ISA controller to operate
in full duplex mode for test pur-
poses. When LOOP = “1”,
loopback is enabled. In combina-
tion with INTL and MENDECL,
various loopback modes are de-
fined as follows:
Read/write accessible only when
STOP bit is set. LOOP is cleared
by RESET.
Disable Transmit. If this bit is set,
the PCnet-ISA controller will not
access the Transmit Descriptor
Ring and, therefore, no transmis-
sions will occur. DTX = “0” will set
TXON bit (CSR0.4) after STRT
(CSR0.1) is asserted. DTX is de-
fined after the initialization block
is read.
Read/write accessible only when
STOP bit is set.
Disable Receiver. If this bit is set,
the PCnet-ISA controller will not
access the Receive Descriptor
Ring and, therefore, all receive
frame data are ignored. DRX =
“0” will set RXON bit (CSR0.5) af-
ter STRT (CSR0.1) is asserted.
DRX is defined after the initializa-
tion block is read.
Read/write accessible only when
STOP bit is set.
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tion 0 must be zero. This register
Non-loopback
External Loopback
Internal Loopback Include
MENDEC
Internal Loopback Exclude
MENDEC
Loopback Mode
Description
Enable
P R E L I M I N A R Y
allows
Am79C960
CSR17: Initialization Block Address Upper
Bit
15-8
7-0
CSR18-19: Current Receive Buffer Address
Bit
31-24
23-0
CSR20-21: Current Transmit Buffer Address
Bit
31-24
23-0
CSR22-23: Next Receive Buffer Address
Bit
31-24
23-0
CRBA
NRBA
CXBA
Name
Name
Name
Name
IADR
RES
RES
RES
RES
is an alias of CSR1. Whenever
this register is written, CSR1 is
updated with CSR16’s contents.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Upper 8 bits of the address of the
Initialization Block. Bit locations
15-8 must be written with zeros.
This register is an alias of CSR2.
Whenever this register is written,
CSR2 is updated with CSR17’s
contents.
Read/Write
when the STOP bit in CSR0 is
set. Unaffected by RESET.
Reserved locations. Written as
zero and read as undefined.
Contains the current receive
buffer address to which the
PCnet-ISA controller will store in-
coming frame data.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the current transmit
buffer address from which the
PCnet-ISA controller is transmit-
ting.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the next receive buffer
address to which the PCnet-ISA
Description
Description
Description
Description
accessible
accessible
only
only