am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 59

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

PCnet-ISA CONTROLLER REGISTERS
The PCnet-ISA controller implements all LANCE
(Am7990) registers, plus a number of additional regis-
ters. The PCnet-ISA controller registers are compatible
with the original LANCE, but there are some places
where previously reserved LANCE bits are now used by
the PCnet-ISA controller. If the reserved LANCE bits
were used as recommended, there should be no com-
patibility problems.
Register Access
Internal registers are accessed in a two-step operation.
First, the address of the register to be accessed is writ-
ten into the register address port (RAP). Subsequent
read or write operations will access the register pointed
to by the contents of the RAP. The data will be read from
(or written to) the selected register through the data port,
either the register data port (RDP) for control and status
status registers (CSR) or the ISACSR register data port
(IDP) for ISA control and status registers (ISACSR)
RAP: Register Address Port
Bit
15-7
6-0
Control and Status Registers
CSR0: PCnet-ISA Controller Status
Bit
15
14
BABL
Name
Name
ERR
RES
RAP
Description
Reserved locations. Read and
written as zeroes.
Register Address Port select.
Selects the CSR or ISACSR
location to be accessed. RAP is
cleared by RESET.
Description
Error is set by the ORing of
BABL, CERR, MISS, and MERR.
ERR remains set as long as any
of the error flags are true. ERR is
read only; write operations are
ignored.
Babble is a transmitter time-out
error. It indicates that the trans-
mitter has been on the channel
longer than the time required to
send the maximum length frame.
BABL will be set if 1519 bytes or
greater are transmitted.
When BABL is set, IRQ is as-
serted if IENA = 1 and the mask
bit BABLM (CSR3.14) is clear.
BABL assertion will set the ERR
bit.
BABL is set by the MAC layer and
cleared by writing a “1”. Writing a
“0” has no effect. BABL is cleared
P R E L I M I N A R Y
Am79C960
13
12
11
MERR
CERR
MISS
by RESET or by setting the
STOP bit.
Collision Error indicates that the
collision inputs to the AUI port
failed to activate within 20 net-
work
terminated transmission (SQE
Test). This feature is a trans-
ceiver test feature. CERR will be
set in 10BASE-T mode during
trasmit if in Link Fail state.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
CERR is set by the MAC layer
and cleared by writing a “1”. Writ-
ing a “0” has no effect. CERR is
cleared by RESET or by setting
the STOP bit.
Missed Frame is set when
PCnet-ISA controller has lost an
incoming receive frame because
a Receive Descriptor was not
available. This bit is the only
indication that receive data has
been lost since there is no re-
ceive descriptor available for
status information.
When MISS is set, IRQ is as-
serted if IENA = 1 and the mask
bit MISSM (CSR3.12) is clear.
MISS assertion will set the ERR
bit.
MISS is set by the Buffer Man-
agement Unit and cleared by
writing a “1”. Writing a “0” has no
effect. MISS is cleared by RE-
SET or by setting the STOP bit.
Memory Error is set when
PCnet-ISA controller is a bus
master and has not received
DACK assertion after 50 s after
DRQ assertion. Memory Error in-
dicates that PCnet-ISA controller
is not receiving bus mastership in
time to prevent overflow/under-
flow conditions in the receive and
transmit FIFOs.
(MERR indicates a slightly differ-
ent condition for the LANCE; for
the LANCE MERR occurs when
READY has not been asserted
25.6
been asserted.)
When MERR is set, IRQ is as-
serted if IENA = 1 and the mask
bit MERRM (CSR3.11) is clear.
s after the address has
bit
times
after
AMD
1-401
chip