am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 68

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

23-12
11-0
CSR42-43: Current Transmit Status and Byte
Bit
31-24 CXST
23-12
11-0
CSR44-45: Next Receive Status and Byte Count
Bit
31-24 NRST
23-12
11-0
CSR46: Poll Time Counter
Bit
15-0
1-410
AMD
CRBC
NRBC
CXBC
POLL
Name
Name
Name
RES
RES
RES
Count
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD2 of the current re-
ceive descriptor.
Read/write accessible only when
STOP bit is set.
Current Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the current transmit
descriptor.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the current trans-
mit descriptor.
Read/write accessible only when
STOP bit is set.
Next Receive Status. This field is
a copy of bits 15:8 of RMD1 of the
next receive descriptor.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD2 of the next receive
descriptor.
Read/write accessible only when
STOP bit is set.
Poll Time Counter. This counter
is incremented by the PCnet-ISA
controller microcode and is used
Description
Description
Description
P R E L I M I N A R Y
Am79C960
CSR47: Polling Interval
Bit
31-16
15-0 POLLINT
CSR48-49: Temporary Storage
Bit
31-0
TMP0
Name
Name
RES
to trigger the descriptor ring poll-
ing operation of the PCnet-ISA
controller.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Polling Interval. This register
contains
PCnet-ISA controller will wait
between successive polling op-
erations. The POLLINT value is
expressed as the two’s comple-
ment of the desired interval,
where each bit of POLLINT rep-
resents one-half of an XTAL1
period of time. POLLINT[3:0] are
ignored. (POLINT[16] is implied
to be a one, so POLLINT[15] is
significant, and does not repre-
sent the sign of the two’s
complement POLLINT value.)
The default value of this register
is 0000. This corresponds to a
polling interval of 32,768 XTAL1
periods. The POLINT value of
0000 is created during the
microcode initialization routine,
and therefore might not be seen
when
RESET.
If the user desires to program a
value for POLLINT other than the
default, then the correct proce-
dure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP in CSR0.
Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000 in CSR47 will be
overwritten with the desired user
value.
Read/write accessible only when
STOP bit is set.
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
reading
Description
Description
the
time
CSR47
that
after
the