am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 41

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

Transmitter Timing and Operation
A 20 MHz fundamental-mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-ISA controller. The crystal input is divided by
two to create the internal transmit clock reference. Both
clocks are fed into the Manchester Encoder to generate
the transitions in the encoded data stream. The internal
transmit clock is used by the MENDEC to internally syn-
chronize the Internal Transmit Data (ITXDAT) from the
controller and Internal Transmit Enable (ITXEN). The in-
ternal transmit clock is also used as a stable bit-rate
clock by the receive section of the MENDEC and
controller.
The oscillator requires an external 0.005% crystal, or an
external 0.01% CMOS-level input as a reference. The
accuracy requirements, if an external crystal is used,
are tighter because allowance for the on-chip oscillator
must be made to deliver a final accuracy of 0.01%.
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO . When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
Receive Path
The principal functions of the receiver are to signal the
PCnet-ISA controller that there is information on the re-
ceive pair, and to separate the incoming Manchester
encoded data stream into clock and NRZ data.
The receiver section (see Receiver Block Diagram) con-
sists of two parallel paths. The receive data path is a
zero threshold, wide bandwidth line receiver. The carrier
path is an offset threshold bandpass detecting line
TSEL LOW:
TSEL HIGH:
DI /RXD
The idle state of DO yields “zero”
differential to operate transformer-
coupled loads.
In this idle state, DO+ is positive
with respect to DO– (logical HIGH).
*Internal signal
Receiver
Reject
Noise
Data
Filter
Receiver Block Diagram
P R E L I M I N A R Y
Am79C960
receiver. Both receivers share common bias networks
to allow operation over a wide input common mode
range.
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width
rejection is proportional to transmit data rate. DC inputs
more negative than minus 100 mV are also suppressed.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
When input amplitude and pulse width conditions are
met at DI , a clock acquisition cycle is initiated.
Clock Acquisition
When there is no activity at DI (receiver is idle), the re-
ceive oscillator is phase-locked to the internal transmit
clock. The first negative clock transition (bit cell center of
first valid Manchester “0”) after IRXCRS is asserted in-
terrupts the receive oscillator. The oscillator is then
restarted at the second Manchester “0” (bit time 4) and is
phase-locked to it. As a result, the MENDEC acquires
the clock from the incoming Manchester bit pattern in
4 bit times with a “1010” Manchester bit pattern.
ISRDCLK and IRXDAT are enabled 1/4 bit time after
clock acquisition in bit cell 5. IRXDAT is at a HIGH state
when the receiver is idle (no ISRDCLK). IRXDAT how-
ever, is undefined when clock is acquired and may
remain HIGH or change to LOW state whenever
ISRDCLK is enabled. At 1/4 bit time through bit cell 5,
the controller portion of the PCnet-ISA controller sees
the first ISRDCLK transition. This also strobes in the in-
coming fifth bit to the MENDEC as Manchester “1”.
IRXDAT may make a transition after the ISRDCLK rising
edge in bit cell 5, but its state is still undefined. The
Manchester “1” at bit 5 is clocked to IRXDAT output at
1/4 bit time in bit cell 6.
Manchester
Decoder
Carrier
Detect
Circuit
16907B-8
IRXDAT*
ISRDCLK
IRXCRS*
AMD
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