am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 63

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

2
1
0
CSR6: RCV/XMT Descriptor Table Length
Bit
15-12 TLEN
11-8
TXSTRTM
JABM
RLEN
Name
JAB
TXSTRT is set by the MAC Unit
and cleared by writing a “1”, set-
ting RESET or setting the STOP
bit. Writing a “0” has no effect.
Transmit
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and will
not set INTR flag in CSR0.
TXS-TRTM is set by RESET and
is not affected by STOP.
Jabber Error is set when the
PCnet-ISA controller Twisted-
pair MAU function exceeds an
allowed transmission limit. Jab-
ber is set by the TMAU cell and
can
10BASE-T mode.
When JAB is set, IRQ is asserted
if IENA = 1 and the mask bit
JABM (CSR4.0) is clear.
The JAB bit can be reset even if
the jabber condition is still
present.
JAB is set by the TMAU circuit
and cleared by writing a “1”. Writ-
ing a “0” has no effect. JAB is also
cleared by RESET or setting the
STOP bit.
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and will not set INTR flag
in CSR0.
JABM is set by RESET and is not
affected by STOP.
Contains a copy of the transmit
encoded ring length (TLEN) field
read from the initialization block
during PCnet-ISA controller in-
itialization. This field is written
during the PCnet-ISA controller
initialization routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. TLEN is only defined
after initialization.
Contains a copy of the receive
encoded ring length (RLEN) read
from the initialization block dur-
ing PCnet-ISA controller initiali-
zation. This field is written during
the PCnet-ISA controller initiali-
zation routine.
only
Description
Start
be
asserted
Mask.
P R E L I M I N A R Y
Am79C960
in
If
7-0
CSR8: Logical Address Filter, LADRF[15:0]
Bit
15-0 LADRF[15:0]
CSR9: Logical Address Filter, LADRF[31:16]
Bit
15-0 LADRF[31:16] Logical
CSR10: Logical Address Filter, LADRF[47:32]
Bit
15-0 LADRF[47:32] Logical
CSR11: Logical Address Filter, LADRF[63:48]
Bit
15-0 LADRF[63:48] Logical
Name
Name
Name
Name
RES
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. RLEN is only defined
after initialization.
Reserved locations. Read as
zero. Write operations should not
be performed.
Logical Address Filter, LADRF
[15:0]. Undefined until initialized
either automatically by loading
the initialization block or directly
by an I/O write to this register.
Read/write accessible only when
STOP bit is set.
LADRF[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
LADRF[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Read/write accessible only when
STOP bit is set.
LADRF[63:48]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register.
Description
Description
Description
Description
Address
Address
Address
AMD
1-405
Filter,
Filter,
Filter,