am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 72

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

CSR84-85: DMA Address
Bit
31-0
CSR86: Buffer Byte Counter
Bit
15-12
11-0 DMABC
1-414
AMD
DMABA
Name
Name
RES
ENTST bit in CSR4 is set, all
writes to this register will auto-
matically perform a decrement
cycle.
When the Bus Activity Timer reg-
ister
enabled, the PCnet-ISA control-
ler will relinquish the bus when
either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occured. When
ENTST (CSR4.15) is asserted,
all writes to this register will auto-
matically perform a decrement
cycle.
Read/write accessible only when
STOP bit is set.
DMA Address Register.
This register contains the ad-
dress of system memory for the
current DMA cycle. The Bus In-
terface Unit controls the Address
Register by issuing increment
commands to increment the
memory address for sequential
operations. The DMABA register
is
PCnet-ISA controller DMA op-
eration. When the ENTST bit in
CSR4 is set, all writes to this reg-
ister will automatically perform
an increment cycle.
This register has meaning only if
the PCnet-ISA controller is in Bus
Master Mode.
Read/write accessible only when
STOP bit is set.
Reserved, Read and written with
ones.
DMA Byte Count Register. Con-
tains a Two’s complement of the
current size of the remaining
transmit or receive buffer in
bytes. This register is incre-
mented by the Bus Interface Unit.
The DMABC register is unde-
fined until written. When ENTST
undefined
(CSR82:
Description
Description
until
DMABAT)
the
P R E L I M I N A R Y
first
Am79C960
is
CSR88-89: Chip ID
Bit
31-28
27-12
11-1
0
CSR92: Ring Length Conversion
Bit
15-0
CSR94:Transmit Time Domain Reflectometry
Bit
15-10
9-0
XMTTDR
RCON
Name
Name
Count
Name
RES
(CSR4.15) is asserted, all writes
to this register will automatically
perform an increment cycle.
Read/write accessible only when
STOP bit is set.
Version. This 4-bit pattern is sili-
con revision dependent.
Part number. The 16-bit code for
the
0000000000000011b.
Manufacturer ID. The 11-bit
manufacturer code for AMD is
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
This register is exactly the same
as the Chip ID register in the
JTAG description.
Ring Length Conversion Regis-
ter. This register performs a ring
length conversion from an en-
coded value as found in the
initialization block to a Two’s
complement value used for inter-
nal counting. By writing bits
15-12 with an encoded ring
length, a Two’s complemented
value is read. The RCON register
is undefined until written.
Read/write accessible only when
STOP bit is set.
Reserved locations. Read and
written as zero.
Time Domain Reflectometry re-
flects the state of an internal
counter that counts from the start
of transmission to the occurrence
of loss of carrier. TDR is incre-
mented at a rate of 10 MHz.
Read accessible only when
STOP bit is set. Write operations
are ignored. XMTTDR is cleared
by RESET.
PCnet-ISA
Description
Description
Description
controller
is