am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 67

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

CSR24-25: Base Address of Receive Ring
Bit
31-24
23-0
CSR26-27: Next Receive Descriptor Address
Bit
31-24
23-0
CSR28-29: Current Receive Descriptor Address
Bit
31-24
23-0
CSR30-31: Base Address of Transmit Ring
Bit
31-24
23-0
NRDA
CRDA
BADR
BADX
Name
Name
Name
Name
RES
RES
RES
RES
controller will store incoming
frame data.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the base address of the
Receive Ring.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the next RDRE address
pointer.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the current RDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the base address of the
Transmit Ring.
Read/write accessible only when
STOP bit is set.
Description
Description
Description
Description
P R E L I M I N A R Y
Am79C960
CSR32-33: Next Transmit Descriptor Address
Bit
31-24
23-0
CSR34-35: Current Transmit Descriptor Address
Bit
31-24
23-0
CSR36-37: Next Next Receive Descriptor Address
Bit
31-0
CSR38-39: Next Next Transmit Descriptor Address
Bit
31-0
CSR40-41: Current Receive Status and Byte
Bit
31-24 CRST
NNRDA
NNXDA
NXDA
CXDA
Name
Name
Name
Name
Name
RES
RES
Count
Reserved locations. Written as
zero and read as undefined.
Contains the next TDRE address
pointer.
Read/write accessible only when
STOP bit is set.
Reserved locations. Written as
zero and read as undefined.
Contains the current TDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
Contains the next next RDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
Contains the next next TDRE ad-
dress pointer.
Read/write accessible only when
STOP bit is set.
Current Receive Status. This
field is a copy of bits 15:8 of
RMD1 of the current receive
descriptor.
Description
Description
Description
Description
Description
AMD
1-409