am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 42

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

1-384
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection
phase-locked clock remains locked on the received sig-
nal. Individual bit cell phase corrections of the Voltage
Controlled Oscillator (VCO) are limited to 10% of the
phase difference between BCC and phase-locked
clock. Hence, input data jitter is reduced in ISRDCLK by
10 to 1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS deassert allows the last bit to
be strobed by ISRDCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of
message.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI /RXD inputs. Input
error is less than 35 mV to minimize sensitivity to input
rise and fall time. ISRDCLK strobes the data receiver
output at 1/4 bit time to determine the value of the
Manchester bit, and clocks the data out on IRXDAT on
the following ISRDCLK. The data receiver also gener-
ates the signal used for phase detector comparison to
the internal MENDEC voltage controlled oscillator
(VCO).
Jitter Tolerance Definition
The MENDEC utilizes a clock capture circuit to align its
internal data strobe with an incoming bit stream. The
clock acquisition circuitry requires four valid bits with the
values 1010b. Clock is phase-locked to the negative
transition at the bit cell center of the second “0” in the
pattern.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter Han-
dling” is:
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Layer Signaling) to PMA
(Physical
The peak deviation approaching or crossing 1/4
bit cell position from nominal input transition, for
which the MENDEC section will properly de-
code data.
AMD
circuit.
Medium
This
Attachment)
circuit
ensures
interface
that
P R E L I M I N A R Y
which
Am79C960
the
connects the DTE to a MAU. The differential interface
provided by the PCnet-ISA controller is fully compliant
with Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).
After the PCnet-ISA controller initiates a transmission, it
will expect to see data “looped-back” on the DI pair
(when the AUI port is selected). This will internally
generate a “carrier sense”, indicating that the integrity of
the data path to and from the MAU is intact, and that the
MAU is operating correctly. This “carrier sense” signal
must be asserted within sometime before end of trans-
mission. If “carrier sense” does not become active in
response to the data transmission, or becomes inactive
before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Descriptor
Ring (TMD3, bit 11) after the packet has been
transmitted.
Differential Input Terminations
The differential input for the Manchester data (DI ) is
externally terminated by two 40.2
one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram
below. The differential input impedance, Z
common-mode input impedance, Z
that the Ethernet specification for cable termination im-
pedance is met using standard 1% resistor terminators.
If SIP devices are used, 39
equivalent value. The CI differential inputs are termi-
nated in exactly the same way as the DI pair.
Collision Detection
A MAU detects the collision condition on the network
and generates a differential signal at the CI inputs. This
collision signal passes through an input stage which de-
tects signal levels and pulse duration. When the signal is
detected by the MENDEC it sets the ICLSN line HIGH.
The condition continues for approximately 1.5 bit times
after the last LOW-to-HIGH transition on CI .
PCnet-ISA
DI+
DI-
Differential Input Termination
40.2
0.01 F
to 0.1 F
is the nearest usable
40.2
ICM
AUI Isolation
Transformer
1% resistors and
, are specified so
IDF
16907B-9
, and the