am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 71

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

11-10XMTSP[1:0]
9-8 XMTFW[1:0]
RCVFW[1:0]
XMTFW[1:0]
XMTSP[1:0]
00
01
10
11
00
01
10
11
00
01
10
11
Transmit Start Point. XMTSP
controls the point at which pre-
amble
commence in relation to the num-
ber of bytes written to the
transmit FIFO for the current
transmit frame. When the entire
frame is in the FIFO, transmis-
sion will start regardless of the
value in XMTSP. XMTSP is given
a value of 10b (64 bytes) after
RESET. Regardless of XMTSP,
the FIFO will not internally over
write its data until at least 64
bytes (or the entire frame if <64
bytes) have been transmitted
onto the network. This ensures
that for collisions within the slot
time window, transmit data need
not be re-written to the transmit
FIFO, and re-tries will be handled
autonomously by the MAC. This
bit is read/write accessible only
when the STOP bit is set.
Transmit
XMTFW specifies the point at
which
based upon the number of write
cycles that could be performed to
the transmit FIFO without FIFO
overflow. Transmit DMA is al-
lowed at any time when the
number of write cycles specified
by XMTFW could be executed
without causing transmit FIFO
overflow. XMTFW is set to a
value of 00b (8 cycles) after hard-
ware
accessible only when STOP bit is
set.
transmit
transmission
RESET.
Bytes Received
FIFO
Bytes Written
Write Cycles
Reserved
Reserved
112
16
32
64
16
64
16
32
DMA
4
8
Watermark.
Read/write
P R E L I M I N A R Y
attempts
stops,
Am79C960
7-0
CSR82: Bus Activity Timer
Bit
15-0 DMABAT
DMABR
Name
DMA Burst Register. This regis-
ter
allowable number of transfers to
system memory that the Bus In-
terface will perform during a
single DMA cycle. The Burst
Register is not used to limit the
number
Descriptor transfers. A value of
zero will be interpreted as one
transfer. During RESET a value
of 16 is loaded in the BURST reg-
ister. If DMAPLUS (CSR4.14) is
set, the DMA Burst Register is
disabled.
When the Bus Activity Timer reg-
ister
enabled, the PCnet-ISA control-
ler will relinquish the bus when
either the time specified in
DMABAT has elapsed or the
number of transfers specified in
DMABR have occured. When
ENTST (CSR4.15) is asserted,
all writes to this register will auto-
matically perform a decrement
cycle.
Read/write accessible only when
STOP bit is set.
Bus Activity Timer. If the TIMER
bit in CSR4 is set, this register
contains the maximum allowable
time that the PCnet-ISA control-
ler will take up on the system bus
during FIFO data transfers in
each bus mastership period. The
DMABAT starts counting upon
receipt of DACK from the host
system. The DMABAT Register
does not limit the number of
transfers
transfers.
A value of zero will limit the
PCnet-ISA controller to one bus
cycle per mastership period. A
non-zero value is interpreted as
an unsigned number with a reso-
lution of 100 ns. For instance, a
value of 51 micro seconds would
be programmed with a value of
510. When the TIMER bit in
CSR4 is set, DMABAT is enabled
and must be initialized by the
user. The DMABAT register is
undefined until written. When the
contains
(CSR82:
of
Description
during
transfers
the
DMABAT)
Descriptor
maximum
AMD
during
1-413
is